Monitor MUX Statistics
To monitor MUX Statistics, click Monitor==>MUX Statistics.
Use the Reset Counters button to restart incrementing values in PMVision only, not on the PortMaster. Click Restore Counters to restore these counters to their real-time values.
To view MUX Statistics simultaneously with other options in the PMVision tree, click New Window.
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PortMaster |
The IP Address or name of the selected PortMaster. |
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Board |
The Board ID. |
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RX Signal Loss Errors |
A receive LOS alarm occurs when the incoming DS3 data is stuck low for more than 1022 clock cycles. Recovery occurs when two or more ones are detected. in the incoming data bit stream. |
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RX AIS Alarm Errors |
Detection mechanism to ensure that the M13E is detecting DS3 framing. |
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RX Out of Frame Errors |
A receive OOF alarm occurs when three out of 16 F-bits are in error utilizing a sliding window of 16 bits, or one or more M-bits are in error in two consecutive frames. Recovery occurs when the F framing pattern of 1001 is detected and the M framing pattern of 010 is detected for two consecutive frames. Recovery takes approximately 0.95 milliseconds. |
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RX Idle Pattern Errors |
If the M13E detects 6 or more errored 4-bit groups of the 1100 pattern per DS3 frame, the M13E exits the RX idle pattern state. A DS3 idle signal (defined in ANSI T1 107a through 1990) is being received by the M13E device if this bit and bits 1 and 0 of this register are set to 1. |
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RX Clock Failures |
A receive DS3 clock faulure alarm occurs when the receive clock is stuck high or low for 30 to 100 DS3 clock periods. Recovery occurs on the first clock transition. |
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TX Clock Failures |
A transmit DS3 clock failure alarm occurs when the transmit input clock is stuck high or low for 30 to 100 DS3 clock periods. Recovery occurs when the first clock transition is detected. |
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F&M Bit Errors |
An eight-bit saturation counter that counts the number of DS3 F bits and DS3 M bits that are in error since the last read cycyle. This counter is inhibited when DS3 loss of signal or out of frame occurs. |
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M Bit Errors |
An eight-bit saturation counter that countes the number of M bits that are in error since the last read cycle. The counter is inhibited when DS3 loss of signal or out of frmame occurs. |
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Parity Errors |
This counter counts the number of P-bit parity errors recieved since the last read cycle. This counter is ingivited during DS3 loss of signal or out of frame times. |